Memristors built with 2-nanometer-thick parts

Phase-change memory seems to offer the best of both worlds: the speed of current RAM with the permanence of a hard disk. While current implementations are too expensive for widespread use, researchers have been doing interesting things with test hardware. Its distinct properties have allowed people to perform calculations and train neural networks, all in memory.

So finding out how to make phase-change memory more efficient could open some new approaches to computing.

This week, a collaboration between scientists at the University of Massachusetts, Amherst and Brookhaven National Lab is publishing a paper describing how it made a tiny set of memristors that acts similar to phase-change memory. The features of the memory are only two nanometers across, and they can be separated by as little as 12nm—below the cutting edge of processor manufacturing. The down sides? So far, the team has only made nine bits at a time, and they’re made using platinum.

On the grid

Key to this new work are tiny sheets of platinum only two nanometers thick—that’s just over 11 atoms of the element. While platinum is rather pricey, the thin sheets provide extremely low resistance. The researchers measured each sheet at about 10,000 times less than the expected resistance of a similar-thickness carbon nanotube. And the authors say they can manufacture the sheets in the appropriate dimensions with a 100-percent efficiency.

These sheets were floated on germanium, allowing them to align with a vertical silicon surface. From there, copper wires are linked to the sheet, which is then covered by aluminum oxide. This leaves the thin, 2nm edge of the sheets pointing up vertically. A second sheet and electrodes are then put in place in the same manner, followed by more aluminum oxide and a third sheet. When the top of this block is polished down, it creates a surface with three parallel lines of platinum, each addressable via its own set of copper electrodes. I’ll refer to these as “wires,” but they’re really just a thin edge of a larger sheet that’s buried inside aluminum oxide.

To make working memristors, two of these blocks were placed with the lines facing each other, creating a tic-tac-toe-like grid with nine points of intersection. In between the blocks, the researchers placed a seven-nanometer layer of a mix of titanium oxide and hafnium oxide.

The copper wires would allow the researchers to activate only one of the three platinum wires in a block at a time. Depending on which of the wires on the opposite block was active, only a single intersection would be active.

Thanks for the memories

Under normal circumstances, the titanium/hafnium oxide layer would act like an insulator and block current flow at the intersection of the copper wires. But give a point sufficient current and a thread of titanium will form, connecting the two bits of platinum. This allows current to flow between them; the difference between the conducting and insulating states could be treated as the difference between a binary one and a zero. And the junction would stay in its new state unless enough current was sent through to reset it.

And it all works. Treating each intersection in the grid as a pixel, the authors set and reset bits in a pattern that spelled out “NANO.”

Assuming the density of their device would scale up, it would be similar to that of 3D flash memory made using a 64-layer process. That works out to be 4.5 terabits per square inch (their units, not ours). And the memristors don’t need anywhere near the sort of depth that the flash does to achieve this.

But could this actually scale beyond nine bits? A lot of potential complications pop up here. One is simply the use of platinum. Sheets that are 11 atoms thick don’t use much of it, and the authors say they can make them with 100-percent efficiency, but it’s still a very expensive material for large-scale manufacturing. So there are clearly going to be advantages to finding a more common metal that can form structures with similar properties.

Then there’s the production. While the processing used is compatible with other semiconductor tech, each step has to be repeated with every additional wire that’s added to the device. If we try to scale this up to useful storage, then it could become time-consuming, and rare problems with the processing are likely to become more significant. If these problems are rare enough, though, then it would be possible to just not use any defective wires and accept a somewhat reduced capacity. That will cut into its storage density a bit, but that’s already quite high.

Perhaps the nicest thing about the hardware, though, is its potential to scale. While the researchers only built three parallel wires, each additional wire would boost the capacity dramatically. A fourth wire would take it from nine bits to 16 and a fifth up to 25 bits. And, with each wire only 12nm from its neighbors, scaling up doesn’t involve an enormous investment in materials and space.

, 2017. DOI: 10.1038/s41565-018-0302-0  (About DOIs).

Latest Articles

Related Articles